1. Field of the Invention
This invention relates to a test pattern structure for endurance test of a flash memory device. In particular, it relates to a test pattern structure that can confirm which function of program, erasure or read is related to degradation of characteristics of the flash memory device.
2. Description of the Related Art
A flash memory device such as a flash EEPROM has both functions of program and erasure. The flash EEPROM must maintain its characteristics although both functions of program and erasure are repeatedly performed. However, as program and erasure operations are performed many times, the characteristics of the flash EEPROM is degraded. Hence, to improve endurance reliability, it is required to find the reason for degradation of characteristics of the flash EEPROM.
In the prior art, to confirm cycling endurance characteristics of program and erasure functions, program and erasure operations are repeatedly performed using a test pattern having a same construct as a pattern of a main chip cell. Since such a test pattern can only confirm the degradation of characteristics of the flash EEPROM, there is disadvantage in that it can not confirm which function of program, erasure or read is related to degradation of characteristics of the flash EEPROM.